2025 – 2026 Teams

Low-Power Wireless Communications & Identification (Going Batteryless)

Team Members: (Left to Right) Michael Wallace, Astin Chang, Saanvika Chanda, Christopher Saetia (Mentor)

Advisor: Greg Durgin

Radio-frequency identification (RFID) tags are low cost (cents per tag) and are often battery-less, consuming only micro-watts of power. Their simplicity allows them to perform simple tasks, such as providing an ID, well. But their low-cost and low-power design makes this technology attractive solution for scalable and robust wireless and sensing networks. This project will examine the next generation of RFID design to meet the complex needs of these networks. The project research can extend to devising extended use cases of RFID tags for sensing, new ways to characterize and test RFID behavior, or novel designs of these low-power tags and communications.

Towards Energy-efficient and compact
SOT-MRAM

Team Members: (Left to Right) Ved Priyadarshi, Siddardh Budamagunta, Taehoon Kim, Yho Han Kim, Ada Gurkas, Md. Nahid Haque Shazon (Mentor)

Advisor: Azad Naeemi

This project will investigate how applying a descending triangular current pulse influences the switching behavior of two-terminal spin–orbit torque magnetic random-access memory (SOT-MRAM) devices. The primary focus will be on how the required out-of-plane spin Hall angle (ζ_z) changes when using such pulse shapes compared to conventional constant or rectangular pulses. Device-level simulations will be used to quantify improvements or trade-offs in switching time and energy consumption. The study will also explore scaling effects, examining how ζ_z and switching performance vary with device dimensions. By understanding these relationships, the project aims to identify design and operation strategies for more energy-efficient and scalable SOT-MRAM.

Unifying the ASHES Analog Computing Toolflow

Team Members: (Left to Right) Pranav Mathews (Mentor) , Ava Thai, Alexander Feng , Oliver Lee , Maithreyi Bharathi, Joseph Shackelford , Catherine Lacey (Mentor)

Advisor: Jennifer Hasler

Tools have proven to be necessary for practically designing and building large, complex electronic systems. Analog computing has lagged behind the current trend of digital computers largely because analog has no comparable toolflow. Our lab developed ASHES, a toolflow for building analog computing ASICs or programming Field Programmable Analog Arrays (FPAAs). This project involves unifying the user front-end to enable reuse of code between FPAA programming and ASIC generation and unifying the backend of the FPAA flow between ashes (our new version) and the old version.

GT Phone Home: Measuring Starlink NTN and Terrestrial Coexistence

Team Members: (Left to Right) Cameron Matson (Mentor), Ryan Elchahal, Advaith Pillai, Shreya Iyer, Aamir Syed, Mia Villavicencio

Advisor: Karthikeyan Sundaresan

Satellites are envisioned to play a major role in future mobile networks as what is called “Non-Terrestrial Networking”. T-Mobile has just announced the ability to send and recieve text messages via satellite using SpaceX’s Starlink constellation over T-Mobile’s spectrum. In this project we will go out into the field to collect RF and networking measurements using phones, a real Starlink terminal, and Software defined radios. There are many open questions about how NTNs and traditional networks will coexist. In particular we will explore the feasibility of using LEO satellites for positioning, navigation, and timing (PNT) in conjunction with terrestrial networks.

Robot Mobile Manipulation

Team Members: (Left to Right) Jing-Chen Peng (Mentor), Shrey Agarwal, Sijuola Samaye, Po Cheng Chen, Sola Ishibashi, Yichen Zhao (Mentor, not pictured)

Advisor: Patricio Vela

This project involves programming a mobile robot to drive around an unstructured environment and manipulate objects to complete tasks, combining classical robotics stacks with state-of-the-art vision language models to perform language-conditioned mobile manipulation.

Convergence criteria and design of SPICE plausible compact modeling framework

Team Members: (Left to Right) Jay Sonawane (Mentor), Vansh Dhawan, Vedang Dugar, Saumya Agarwal, May Ming

Advisor: Shimeng Yu

Compact models are very important for understanding circuit and system level implementations in hardware. However, the more physical or complex a comapct model is, the difficulty of convergence in large circuit or array level simulations hinder understanding of certain physical behaviors in device to circuit implications. This project focuses on designing, implementing, and testing convergence-friendly compact models in Verilog-A, both physics-based and machine-learning-based.

Enriching the world of High Level Synthesis: extended construction for HLSFactory

Team Members: (Left to Right) Callie Hao (Faculty Advisor), Stefan Abi-Karam (Mentor), Justin Zhou, Tanmay Shukla, Kaushik Chandana, Hanqiu Chen (Mentor, not pictured)

Advisor: Callie Hao

We are interested in building large-scale digital design datasets for AI applications in chip design. Mainly, the project focuses on curating high-level synthesis (HLS) designs from the academic community to integrate into our previous hardware design dataset effort, HLSFactory. Time allowing, we are also interested in creating more synthetic HLS designs using LLMs, as well as new cases for benchmarking LLMs on HLS design.